1. Field of the Invention
The present invention relates generally to successive approximation register analog-to-digital converters (SAR ADCs).
2. Description of the Related Art
The conventional SAR ADC 20 of FIG. 1 comprises a sampler 22 that is coupled to a switched capacitor (or charge distribution) digital-to-analog converter (CDAC) 24, a successive approximation register (SAR) 26, a comparator 28 that is coupled between the CDAC 24 and the SAR 26 and a timing and control module 30 that is coupled to the sampler 22 and the SAR 26.
The CDAC includes an array of capacitors whose capacitances are binarily weighted. For example, a most-significant capacitor has a capacitance C/2, a next most-significant capacitor has a capacitance C/4and so on. The least-significant capacitor has a capacitance of C/2n and is duplicated by a capacitor 31 so that the total array capacitance is C. Accordingly, binary division is realized when each capacitor""s capacitance is successively compared to the array capacitance (e.g., as a capacitive divider, capacitance C/2 is xc2xd that of the array capacitance C, capacitance C/4 is xc2xc that of the array capacitance and so on).
The capacitor top plates (e.g., the top plate 32) are coupled to one differential port 33 of the comparator 28 and their bottom plates (e.g., the bottom plate 34) are selectively coupled through bottom-plate switches 35 to a sample (IN) from the sampler 22, to a first reference signal which is generally that applied to the comparator""s other differential port 36 (e.g., GND) and to a second reference signal (REF) which is generally the full scale range of the SAR ADC 20. The bottom-plate switches 35 respond to control signals 37 from the SAR 26 which also controls an output switch 38 that selectively causes the CDAC""s analog output signal to be coupled to the comparator 28 or to ground.
In operation of the SAR ADC, an analog signal is presented to the input port 39 of the sampler (e.g., a sample-and-hold amplifier (SHA)) and, in response to a hold signal from the timing and control module, the sampler provides an input signal sample Sin to the input port (IN) of the switched capacitor DAC 24. Initially, the output switch 38 applies a ground to all of the top plates 32 and the bottom-plate switches 35 couple the input signal sample Sin to all of the bottom plates 34 so that all capacitors acquire a potential of Sin. Subsequently, the SAR causes the output switch 38 to couple the top plates 32 to the comparator""s differential port 33 and the switches 35 to couple the bottom plates 34 to GND so that a potentialxe2x88x92Sin appears at the comparator""s differential port 33.
The SAR 26 then causes the bottom plate of the capacitor C/2 to be switched to REF and a capacitive divider ratio of (C/2)/C changes the potential at the differential port 33 to REF/2xe2x88x92Sin. This latter signal is illustrated in the diagram 40 of FIG. 2A. If the comparator output indicates that REF/2xe2x88x92Sin is below GND, the SAR leaves the bottom plate of capacitor C/2 coupled to REF. If the comparator output indicates that REF/2xe2x88x92Sin is above GND (as in FIG. 2A), the SAR returns the bottom plate to GND. This process is repeated with the next capacitor C/4 which changes the potential at the differential port 33 to REF/4-Sin. FIG. 2A illustrates that REF/4xe2x88x92Sin is less than GND so that the SAR leaves the bottom plate of capacitor C/4 coupled to REF.
This process is repeated for the remaining capacitors to complete a successive approximation sequence that causes the potential on the top plates to approximate the potential at the comparator""s other differential port 36 (i.e., GND) and thereby causes the control signals 37 to become a binary weighted version of the input sample Sin. That is, the control signals form a successive approximation word that corresponds to the input sample Sin and is delivered over a digital output bus 41. The conversion process may be controlled through a control bus 42 that couples the timing and control module 30 to external components. Because the above-described operation is based upon successive approximation words from the SAR, this type of ADC is generally referred to as a SAR ADC.
A principal advantage of CDACs is that their accuracy and linearity are primarily determined by photolithography which defines capacitor plate areas to thereby establish capacitances and capacitance matching. In addition, small calibration capacitors can be added and switched under control of the SAR 26 to improve accuracy and linearity and eliminate the need for ADC trimming routines (e.g., thin-film laser trimming). CDACs also reduce static currents and DC power dissipation and provide a high degree of temperature stability because the temperature tracking between switched capacitors is typically quite high (e.g., better than 1 ppm/xc2x0 C.).
The SAR ADC 20 is an example of a single-ended SAR ADC configuration. In another single-ended configuration, the calibration capacitors are in the form of a second CDAC which is also coupled to the differential port 33 of the comparator 28 of FIG. 1. The second CDAC provides analog correction signals that compensate for capacitance mismatches in the first CDAC 24. The switches (e.g., metal-oxide semiconductor (MOS) switches) of single-ended SAR ADC configurations typically inject error charges into the comparator (28 in FIG. 1) and these switching-induced errors are difficult to eliminate.
Accordingly, another conventional SAR ADC configuration adds a xe2x80x9cdummyxe2x80x9d CDAC and couples it to the comparator""s other differential port (36 in FIG. 1) and drives the dummy""s capacitor array with a fixed reference (e.g., GND). This creates a pseudo-differential configuration which injects similar error charges into the differential input of the comparator so that the errors are substantially reduced by the common-mode rejection of the comparator. Because it adds a third CDAC, this pseudo-differential configuration requires substantial integrated circuit area.
Circuit area is reduced in a different pseudo-differential configuration in which the dummy CDAC at the other differential port (36 in FIG. 1) provides the analog correction signals and accordingly, the second CDAC at the differential port 33 can be eliminated.
Pseudo-differential configurations reduce switching-induced errors but their signal-to-noise ratio (SNR) is less than desired. The SNR is substantially improved in a fully-differential configuration in which first and second CDACs are coupled differentially to the comparator and are both driven with successive approximation signals from the SAR so their analog signals to the comparator (28 in FIG. 1) change in opposite and equal steps during the successive approximation sequence.
Exemplary differential signals are illustrated in the diagram 44 of FIG. 2B where REF/2xe2x88x92Sin is compared to xe2x88x92REF/2+Sin. Successively, REF/4xe2x88x92Sin is compared to xe2x88x92REF/4+Sin and so on. Because xe2x88x92REF/2+Sin does not exceed REF/2xe2x88x92Sin, the SAR returns the bottom plates of capacitors C/2 of the first and second CDACs to GND. In contrast, xe2x88x92REF/4+Sin exceeds REF/4xe2x88x92Sin, so that the SAR leaves the bottom plates of capacitors C/4 of the first and second CDACs coupled to REF.
In a fully-differential configuration, the sampler 22 of FIG. 1 would have a differential input port 46 and the differential signals would vary from positive full scale of REF and GND respectively at the upper and lower sides of the port to negative full scale of GND and REF respectively at the upper and lower sides. The input signal range of a fully-differential configuration is therefore effectively doubled while noise has not been substantially changed so that the SNR is also substantially doubled. Because both CDACs are active in this fully-differential configuration, a third CDAC must be added to obtain the analog correction signals which increases converter size and cost.
The present invention is directed to quasi-differential successive-approximation methods and structures for converting analog signals into corresponding digital signals. These methods and structures realize the signal-to-noise improvements of fully-differential SAR ADCs and the calibration accuracy improvements of pseudo-differential SAR ADCs. Structures of the invention operate in a fully-differential mode to establish more-significant bits of the corresponding digital signals and in a pseudo-differential mode to establish the less-significant bits.
An SAR ADC embodiment includes a pair of binarily-weighted capacitor arrays and a third binarily-weighted capacitor array. The pair of capacitor arrays generate differential approximation signals and each includes a least capacitor. The third capacitor array generates single-ended approximation signals and has a greatest capacitor that substantially equals the least capacitor.
The differential approximation signals include a least differential approximation signal and the single-ended approximation signals include a greatest single-ended approximation signal that substantially equals the difference of the least differential approximation signal.
A calibration capacitor array is preferably included to generate correction signals that complement the differential approximation signals.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from following description when read in conjunction with the accompanying drawings.